The present invention relates to computer-aided design tools and techniques for the interactive design, implementation, and simulation of complex circuits and systems, particularly digital devices, modules and systems.
Present day state-of-the-art design technique, logic synthesis, is really only a mapping between different levels of physical abstraction.
One of the most difficult problems in design automation is the inability to get timing closure at even the gate level effectively. This forces designers to do two designs: logic design and timing design. Otherwise, the designer simply over-designs the circuits, because the best case timing is much different from the worst case timing. In other cases, designers insist on control of device layout so that they can evaluate all of the tradeoffs between implementation and timing.
Present computer aided design (CAD) systems for the design of electronic circuits, referred to as ECAD or Electronic CAD systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. Typically, five major software program functions run on the ECAD system: a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram using the display screen, generating a net list (summary of connections between components) in the process. The logic compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification and simulation into a schematic object file or files whose format(s) is(are) optimized specifically for those functions. The logic verifier checks the schematic for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if any such design problems exist. The logic simulator takes the schematic object file(s) and simulation models, and generates a set of simulation results, acting on instructions initial conditions and input signal values provided to it either in the form of a file or user input. The layout program generates data from which a semiconductor chip (or a circuit board) may be laid out and produced. An overall object of an ECAD system is to provide a logic synthesis function.
The Modular Design Environment (MDE) produced by LSI Logic Corporation of Milpitas, Calif., is a suite of software tools for computers running the UNIX operating system. MDE comprises a schematic editor (LSED) and a simulator (LDS), among other software programs, and provides an example of commercially available tools of the aforementioned type. Another example of a schematic editor, schematic compiler, and schematic simulator may be found in the SCALDstation produced by Valid Logic Systems, Inc. of Mountain View, Calif.
VHDL, or VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, is a recently developed, higher level language for describing complex devices. The form of a VHDL description is described by means of a context-free syntax together with context-dependent syntactic and semantic requirements expressed by narrative rules. VHDL is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987), and is also known as MIL-STD-454, Regulation 64.
VHDL represents an important step forward in design specification languages because the semantics, or intent, of the language constructs are clearly specified. In theory, VHDL unambiguously describes a designer""s intended system or circuit behavior, in syntactic terms. The xe2x80x9cdesign entityxe2x80x9d is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a sub-system, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between. A xe2x80x9cconfigurationxe2x80x9d can be used to describe how design entities are put together to form a complete design.
VHDL supports three distinct styles for the description of hardware architectures. The first of these is xe2x80x9cstructuralxe2x80x9d description, wherein the architecture is expressed as a hierarchical arrangement of interconnected components. The second style is xe2x80x9cdata-flowxe2x80x9d description, in which the architecture is broken down into a set of concurrent register assignments, each of which may be under the control of gating signals. This description subsumes the style of description embodied in register transfer level (RTL) descriptions. The third style is xe2x80x9cbehavioralxe2x80x9d description, wherein the design is described in sequential program statements similar to a high-level programming language. In the main hereinafter, the behavioral description style is discussed. However, all three styles may be intermixed in a single architecture.
A methodology for deriving a lower-level, physically-implementable description, such as a RTL description of the higher level (e.g. VHDL) description, via an intermediate rule-based tool such as Prolog, is disclosed herein.
Prolog is a programming language based on predicate logic. It can be used for xe2x80x9cintelligentxe2x80x9d tasks like mathematical theorem proving. A Prolog program is a set of rules which define the relationships among objects. The general form of a Prolog rule is a xe2x80x9chornxe2x80x9d clause, in which a specified xe2x80x9cgoalxe2x80x9d is true if certain conditions are true. Execution of a Prolog program involves finding a proof for the goal in question, using unification and resolution. An important aspect of Prolog employed in the present invention is xe2x80x9cterm_expansionxe2x80x9d, which converts predefined rules into ordinary Prolog clauses.
The schematic editor of the ECAD system is usually an interactive software tool which enables the user to select from a number of circuit elements which will be graphically displayed upon a graphical/text display device, hereinafter referred to as the display screen, connected to the computer. These displayed elements may then be interconnected by lines representing wires drawn on the display screen by the user through interaction with the computer via a position input device, which may be a pointing device such as a mouse, trackball, joystick, graphic tablet, or keyboard used to enter coordinates on the display screen and commands to the software tool. The circuit elements and their interconnecting wires form a schematic diagram which is viewed either in whole or in part on the display screen. As the schematic diagram is constructed on the display screen, the computer represents these elements in a storage medium, which may be a memory or a mass storage device such a magnetic disk drive. These representations, taken as a group, form a numerical representation of the schematic which has been entered by the user in a standardized form which is understood by the schematic editor. Typically, this form has been optimized for the entry and modification of schematic information.
Often, schematic editors allow for hierarchical design whereby a previously created and stored circuit may be recalled and viewed and used as a macro-level component in other circuits. Multiple instances of such macro-level components may be included in a higher-level schematic diagram. The schematic editor creates data structures effectively replicating the macro-level component. The higher-level schematic may further be incorporated as a macro-level component into yet higher-level schematic diagrams, and so on.
Typically, the form of user interaction with the schematic editor is an object-oriented screen display whereby the user thereof may manipulate objects on the screen through the use of a pointing device. A pointing device is any device through the use of which a user may xe2x80x9cpointxe2x80x9d to and identify objects on a display screen. Such object-oriented interfaces are well known to those skilled in the art. One example of such and interface is the Macintosh Finder for the Apple Macintosh computer, both produced by Apple Computer, Inc. Another example of such an interface is that of Microsoft Windows, produced by Microsoft Corp. of Redmond, Washington.
In order to simulate the performance of the circuit, it is necessary to run a simulator. A simulator is a software tool which operates on: a digital representation, or simulation model of a circuit, a list of input stimuli representing real inputs, and data about the performance characteristics of the represented circuit elements; and generates a numerical representation of the response of the circuit which may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. Typically, the graphical presentation is designed to produce an image similar to what one would see on an oscilloscope or logic analyzer screen monitoring a real circuit connected as described in the schematic diagram if the real inputs represented by the list of input stimuli were applied. The simulator may be run either on the same computer which is used for schematic entry, or on another piece of electronic apparatus specially designed for simulation. Simulators which run entirely in software on a general purpose computer, whether the same as or different from the one used for schematic entry, will hereinafter be referred to as software simulators. Simulations which are run with the assistance of specially designed electronic apparatus will hereinafter be referred to as hardware simulators. An example of a such a hardware simulator is described in U.S. Pat. No. 4,587,625, entitled PROCESS FOR SIMULATING DIGITAL STRUCTURES. Usually, software simulators perform a very large number of calculations compared to the number required for schematic entry and operate slowly from the user""s point of view. In order to optimize performance, the format of the simulation model is designed for very efficient use by the simulator. Hardware simulators, by nature, require that the simulation model comprising the circuit description and its performance parameters be communicated in a specially designed format. In either case, a translation process is required.
Simulation is often provided by utilizing simulation models at one or more of several different levels. Component-level models attempt to describe the exact behavior of a specific component, such as a gate or transistor, when it is acted upon by a stimulus or stimuli. Behavioral-level models provide a simplified model of extremely complicated devices, such as a microprocessor, or an operational amplifier. Such models, if simulated exactly on a transistor by transistor basis, would become prohibitive in terms of the size of their descriptions and the number of calculations and amount of computing time required to completely simulate their function. In response to this, the behavioral-level model provides a logical or mathematical equation or set of equations describing the behavior of the component, viewed as a xe2x80x9cblack boxxe2x80x9d. Such models may either provide a very complete and accurate description of the performance of the modeled device, or a simple description of the types of signals one might expect the modeled device to produce. For example, a behavioral model of a microprocessor might provide the user with the capability of issuing various types of bus cycles, but not the capacity to actually simulate the execution of a program. Circuit-level models typically comprise a plurality of component-level and/or behavioral-level models and the descriptions of their interconnections for the purpose of simulating the performance of a complete circuit comprising a number of interconnected components. Simulations of hierarchical designs require that the included macro-level components also be simulated. Circuit-level or behavioral-level models of the macro-level components may be used to simplify this task.
The simulation model used by the simulator is usually derived from the output of the schematic editor by a schematic compiler, also making use of information about performance characteristics of the circuits, often stored in simulation libraries. Simulation libraries contain simulation characteristics of numerous circuit components and are typically maintained in files on the computer""s on-line storage devices. The schematic compiler is a software tool which interprets the circuit element and interconnection information generated by the schematic editor and the performance characteristics stored in the simulation libraries, and reorganizes and translates them into the simulation model for the circuit. Occasionally, either the simulator or the schematic editor includes the function of a schematic compiler, in which case, separate compilation is not required.
Simulators often allow several different types of simulation. One type is a complete simulation run, where an initial set of conditions is specified, a set of input stimuli is defined and the duration of the simulated run is specified. The simulator then operates on the data and produces a file of the results which may be displayed. Another type of simulation, similar to the complete simulation run is an event-terminated run, whereby the simulation is run until a certain pre-specified event occurs in the simulation results. The simulation may be terminated immediately at that point, or run for some simulated duration afterwards. One final type of simulation run is a stepped simulation run, whereby the current simulation may be xe2x80x9csteppedxe2x80x9d by one unit of time, or one clock cycle, or some other similar criterion.
The process of designing an electronic circuit on a typical ECAD system is done in several discrete steps. A schematic diagram of the circuit is entered interactively through the use of a schematic editor which produces a digital representation of the circuit elements and their interconnections. The user of the ECAD system then prepares a list of input stimuli representing real input values to be applied to the simulation model of the circuit. This representation is then compiled by a schematic compiler and translated into a form which is best suited to simulation. This new, translated representation of the circuit is then operated upon by a simulator, which produces numerical output analogous to the response of a real circuit with the same inputs applied. This output is then usually presented to the user in a graphical fashion. By viewing the simulation results, the user may then determine if the represented circuit will perform correctly when it is constructed. If not, he may then re-edit the schematic of the circuit using the schematic editor, re-compile and re-simulate. This process is performed iteratively until the user is satisfied that the design of the circuit is correct.
While the design process outlined herein is significantly faster and less error prone than manual design, the user must still go through the design process in a number of discrete, disjointed steps. The design process is broken into two or three separate thought processes. First, the user must enter the schematic into the computer using a schematic editor. Second, the user completes the schematic entry process and instructs the appropriate software tool (schematic editor, schematic compiler, or simulator) to prepare the design for simulation. Third, the user must create simulation stimuli, usually with the assistance of yet another software tool, and instruct the simulator to apply these stimuli to the simulation model of the circuit being designed. The results are viewed by the user, who then makes a judgement about whether the design is performing correctly.
In modern digital systems, designs incorporating 20,000 logic gates or more are not uncommon. Also, in modern analog electronic systems, especially where the function being designed is intended to be incorporated into an integrated circuit, it is not uncommon to encounter designs comprising many hundreds of transistors and other electronic devices. These designs, due to their complexity, present a need for frequent simulation of the circuit being designed in small parts before it is simulated as a whole. This is necessary because errors in a small portion of the circuit are easy to detect when that small portion is simulated in isolation. On the other hand, when the entire circuit is simulated, compound errors may occur which mask other errors. Further the enormity of modern circuit complexity makes the errors in the small portion of the circuit difficult to recognize.
This need for frequent, partial simulation is somewhat frustrated by current ECAD systems which require the user to break his train of thought in the design process and to move from one tool to the next. Some ECAD systems have begun to attack this problem by providing xe2x80x9cwindowedxe2x80x9d displays, whereby the user may display the output of several software programs at once on different portions of the display screen. This design environment, however is still not fully interactive. In order to simulate small portions of a circuit, the user may need to design special test circuits incorporating those small portions of the circuit and simulate them in isolation.
It is therefore an object of the present invention to provide an improved ECAD system whereby the characteristics of schematic editor, schematic compiler, and simulator are all presented to the user in a fashion such that they appear as a single, integrated function.
It is a further object of the present invention to allow portions of a circuit which is being designed on such an improved ECAD system to be simulated in isolation without requiring that those circuit portions be copied to another schematic, regardless of whether or not the overall schematic diagram has been completed, and regardless of whether or not the circuit portion has other connections.
It is a further object of the present invention to allow the user to view full or partial simulation results on the display screen representation of the schematic as it is being edited on the improved ECAD system.
It is a further object of the invention to enable the user to view state, performance, loading, drive strength or other relevant data (hereinafter, xe2x80x9cstatexe2x80x9d data) in display areas immediately adjacent to the schematic object to which it pertains.
It is a further object of the invention to enable the user to perform simulator setup on the schematic diagram by using point and select techniques to identify items to be simulated, input values, override values, and points to be monitored.
It is a further object of the invention to enable the user to create state tables for circuits, portions of circuits, or components.
It is a further object of the invention to enable the user to store the interactive state data for viewing at another time.
It is a further object of the invention to enable the user to create macros to move through the simulation in defined steps (of xe2x80x9cnxe2x80x9d time units of the lowest system granularity), or to cycle a clock.
It is a further object of the invention to enable the user to pop up data sheets or any library element being used, and further to allow the user to define his/her own data sheets and to allow these to be popped up in the schematic editor environment.
It is a further object of the present invention to provide a methodology for deriving a valid structural description of a circuit or system from a behavioral description thereof, thereby allowing a designer to work at higher levels of abstraction and with larger, more complex circuits and systems.
It is a further object of the present invention to provide a technique for automatically translating behavioral descriptions of a circuit or system into physical implementations thereof.
It is a further object of the present invention to provide an improved logic synthesis function for an ECAD system.
It is further object of the invention to raise the level of design validation from a structural (net list) level to a behavioral level.
It is a further object of the invention to provide a more standardized design environment, thereby alleviating the need for cross-training between different design platforms and allowing resources to be directed more towards synthesis and testability.
It is a further object of the invention to provide a technique interactive design, synthesis, simulation and graphical display of electronic systems.
It is a further object of the present invention to provide a technique for indicating the source of design rule violations in a logic synthesis or design process to a user.
It is a further object of the present invention to provide a technique for automatically providing suggestions to a user about possible alterations or corrections to a design or design description of an electronic system which violates design rules.
It is a further object of the invention to accomplish the above objects in a manner compatible with the design of board-level systems, multi-chip modules, integrated circuit chips, and ASICs using core modules.
It is a further object of the invention to accomplish the above objects independently of scale, complexity, or form factor of the electronic system.
According to the invention, there is provided an electronic CAD system operated with a suite of software tools for enabling a designer to create and validate a structural description and physical implementation of a circuit or system (hereinafter, xe2x80x9cdevicexe2x80x9d) from a behavior-oriented description using a high-level computer language. The methodology includes the following steps:
First, the designer specifies the desired behavior of the device in a high-level language, such as VHDL. The description includes high-level timing goals.
Next, in a xe2x80x9cbehavioral simulationxe2x80x9d step, starting with the VHDL behavioral description of a design, the designer iterates through simulation and design changes until the desired behavior is obtained.
Next, in a xe2x80x9cpartitioningxe2x80x9d step, the design is partitioned into a number of architectural blocks. This step is effectively one of exploring the xe2x80x9cdesign spacexe2x80x9d of architectural choices which can implement the design behavior. Links to the physical design system enable high level timing closure by constraining the feasible architectural choices to those which meet the high-level timing and area (size) goals. This is a key step because it represents the bridge between the conceptual level and the physical level. A second function of this step is to direct the various architectural blocks to the appropriate synthesis programs.
Next, in a xe2x80x9clogic synthesisxe2x80x9d step, a number of separate programs are used to efficiently synthesize the different architectural blocks identified in the partitioning step. Those blocks having highly regular structures or well understood functions are directed to specific synthesis tools (e.g. memory or function compilers). Those blocks with random or unstructured logic are directed to more general logic synthesis programs. The output of this step is a net list of the design.
Next, in a xe2x80x9cphysical simulationxe2x80x9d step, the gate-level design description is simulated, comparing the results with those from the initial behavioral simulation. This provides a check that the circuit implementation behaves as intended, and that the timing goals are achieved.
Optionally, the design is back-annotated to ensure that other physical design limitations, such as capacitive loads and parasitics, are not exceeded.
Finally the design is input to existing software systems which control the physical implementation of the design, such as in an ASIC (Application Specific Integrated Circuit) device.
An important feature of the present invention is that, as with all top-down design approaches, the foregoing is a process of architectural refinement in which design realization moves down through levels of abstraction. The characteristics of VHDL and the disclosed methodology enable this process to occur without losing the intent and meaning present at higher levels. This is the key to automating the process.
Another important feature is that the partitioning step, or partitioner, in effect, uses high-level timing information extracted from the chip floorplan to constrain the design into the feasible architectural choices which meet the high-level timing goals. These constraints are key to allowing the process to converge to specific physical embodiments.
Another important feature is that the methodology enables timing closure without going to actual layout, solving one of the most difficult problems in design automation today, namely the inability to get timing closure at even the gate level effectively which in the past has forced designers to create two designs: a logic design and a timing design. Using the methodology disclosed herein, timing closure can be obtained by using a form of back annotation which will extract timing data from floorplanning-level layouts and then incorporate this data into the I/O (Input/Output) ports of the VHDL behavioral description.
According to an aspect of the invention, the behavioral (VHDL) description of the device is interpreted by attaching one or more semantic rules to each of the syntactic rules underlying the behavioral description. This is accomplished (such as via Prolog) using a xe2x80x9csyntax attributed treexe2x80x9d.
According to the invention, the electronic CAD system comprises a computer processor, mass storage, a display screen, means for user input, and means for circuit simulation. The electronic hardware of the means for simulation may comprise the ECAD system""s computer, one or more general purpose computers interfaced to the ECAD system""s computer, one or more hardware simulators interfaced to the ECAD system""s computer, or any combination of these. The user interacts with the ECAD system through the use of an object-oriented user interface, whereby the user may create, select, move, modify and delete objects on the display screen, where objects may represent circuit components, wires, commands, text values, or any other visual representation of data. The graphical and software techniques of interacting with a user on such an object-oriented user interface are well known to those skilled in the art and need not be elaborated upon in this discussion.
A component database resides on the ECAD system""s mass storage. This database comprises a number of data objects: graphical symbols, connection information, timing parameters, and simulation models corresponding to various electronic components. These data objects contain all of the information necessary to display, interconnect, and edit schematic symbols on a graphical display screen. The simulation model data objects contain the behavioral data corresponding to the components represented by the graphical objects such that the simulator may produce results closely approximating those that would be observed if real components were used and measured on standard laboratory instrumentation.
Five major software program functions run on the ECAD system: a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram using the display screen, generating a net-list (summary of connections between components) in the process. The logic compiler takes the net list as an input, and using the component database puts all of the information necessary for layout, verification and simulation into a schematic object file or files whose format(s) is(are) optimized specifically for those functions. The logic verifier checks the schematic for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if any such design problems exist. The logic simulator takes the schematic object file(s) and simulation models, and generates a set of simulation results, acting on instructions initial conditions and input signal values provided to it either in the form of a file or user input. The layout program generates data from which a semiconductor chip (or a circuit board) may be laid out and produced.
These programs are typical of similar, discrete programs existing in the current art, but are slightly modified (improved in their functionality) in the source of their control information. The editor""s user interface is extended such that the simulator functions may be requested by the user. It is further modified such that whenever a change is made to the schematic, the editor updates its output files (net list, etc.) and signals the logic compiler to re-compile the schematic using the new data. The logic compiler is modified to accept such commands directly from the editor, rather than from user input. The simulator is modified such that it can accept directly from the editor: requests for simulation runs, initial data, signal data, and other information usually entered by the user via the keyboard and/or pointing device. It is further modified to signal the editor that it has completed a simulation operation, and to provide its results in the form of a data structure, either in memory or in a disk file, rather than to the display screen. The logic verifier is also modified such that it interacts with the editor directly, rather than with the display screen and keyboard/pointing device.
Further according to the invention, the editor causes the logic compiler to re-compile the schematic each time a graphical object (schematic symbol) is added, modified, or deleted, and each time a connection is made, changed or removed. In this way, the editor ensures that the net-list and simulation structures are always current and representative of the schematic diagram as displayed on the ECAD system""s graphical display screen.
At any time, the user may instruct the editor to create areas on the display screen adjacent to selected schematic symbol connection points (pins) or on connection nets (wires). By conventions already in place in all editors, compilers, and simulators, these connection points and/or connection nets are uniquely identifiable. The user may specify that these data areas are to contain textual state data, or graphical state data. Next the user may identify certain signal values to be injected into the circuit representation. Ordinarily these would be input signals, but for simulation of part of the schematic, it is possible to override the outputs of selected schematic object to force special conditions to exist on a net, or to force signals into a particular input connection point on a schematic object, effectively overriding its connection. It is also possible for the user to indicate that only certain components are to be compiled and simulated, thus improving the compile and simulation times. This is accomplished by one of two means: either subset net-list and object files are created, reducing the amount of data to be handled by the logic compiler and logic simulator, or software flags are provided in the data structures indicating which data objects are to be considered active, allowing the logic compiler to selectively compile the schematic and allowing the logic simulator to selectively simulate the schematic.
All of the user input occurs by pointing with the pointing device and selecting connection nodes, nets or devices and issuing commands which affect the selected object""s numerical parameters. Each data object (schematic symbol, connection net (wire), and connection point (pin)) has special parameters which allow it to be made eligible or ineligible for compile and/or simulation, and to have some or all of its other parameters overridden for the purposes of simulation.
When the user wishes to perform a simulation he issues a command which is relayed by the editor to the simulator. The simulator performs a simulation run according to the user""s specification and places the simulation results into a data structure. It signals the editor that the simulation is complete and then fills in the results on the screen, according to the user""s display specification. The user may specify a complete simulation run from a set of initial conditions or a simulation stepped run which continues from the last simulation""s ending point. In the event of a complete simulation run, a new simulation results data structure is created and filled in. In the event of a stepped run, the simulator appends new simulation data to the end of the previously created simulation results data structure.
Simulators, by their nature, must maintain the last state (history) of every node for every enabled component in the schematic. However, this history is kept only for those signals requested. This is done to minimize the amount of data storage required. It is possible to request that the history be maintained for all nodes at the expense of some amount of additional memory (or disk space) required.
When the editor receives notification from the simulator that the simulation run is finished, it displays the simulation data on the screen according the specifications for the display areas that the user has requested. If it is a textual display area, then the last state of the node is written into the allocated display area. If it is a graphical (timing diagram) display area, then the history data is presented in the allocated display area in the form of a timing diagram. In either case, the user can step through the state data back from the end point to any previous point in the simulation from the beginning of the session.
The editor may also create, at the user""s request, an area on the screen for the presentation of a state table. The user identifies the signals to be monitored and identifies the simulation conditions. The editor then draws a table on the screen and headings corresponding to the monitored signals"" names, and requests a series of stepped simulations. After each step, the editor records the last state data into columns under the signal name headings, thus creating a state table of the type seen in component specifications.
The techniques described hereinabove for electronic system synthesis, graphical design of an electronic system, simulation and display are independent of the type of electronic system being designed and may be applied with equal facility to multi-board systems, board-level designs, ASICs, custom integrated circuits, portions of systems, or multi-chip modules.
According to an aspect of the invention, the techniques of electronic circuit synthesis and simultaneous graphical editing and display can be used in combination to provide a user with means for viewing a behavioral synthesis of an electronic system in progress, and to simulate the all or a portion of the electronic system and to view signals within the electronic system.
According to another aspect of the invention, design rule violations (e.g., timing violations detected during synthesis) flagged by the synthesis process can be presented to the user by display the portion of the electronic system involved in the violation in schematic diagram form, and presenting simulation results which illustrate the violation on the schematic diagram.
According to another aspect of the invention, an expert system can be used to analyze the electronic system and the design rule violation, and to suggest to the user possible alterations or corrections to the design of the electronic system which would eliminate or correct the design rule violation.
Other objects, features and advantages of the invention will become apparent in light of the following description thereof.